The chip behind the mask

The dictionary gives the meaning of the word “mask” as a “false face used among primitive races to exercise witchcraft and sorcery.” The word “mask” also denotes a “covering worn on the face to conceal identity.” In realms far removed from masquerade balls, Infineon also uses masks – but, as one might well expect, for entirely different purposes.

The masks in our field define the structures and hence the functions of the chip. Structures signify the elementary components of a chip, i.e. transistors, diodes, resistors, capacitors and their interconnections. These elementary components, in turn, have sub-structures such as doping areas or isolation layers, which are ultimately defined by the masks.

Masks are projection patterns and are used in the photolithographic exposure units in the front-end fab. They are glass plates made of high-purity quartz glass provided with a thin layer of chrome. The light-proof chrome layer defines the structures transferred to the wafer by an exposure process. Very stringent demands on the material are made in terms of purity, transmissivity and planarity. Photo masks have to be absolutely flawless because any defect would find itself on each wafer during exposure. So it is that the mask is the blueprint with which many millions of identical chips are produced. The structures of the mask are about four to five times larger than the structure to be created on the wafer, i.e. the structures on the masks are scaled down by the factor 4 to 5 as a result of the exposure process.

A varying number of masks are required for one chip, depending on complexity. Chips for power electronics or discrete components are of low complexity and get by with some 10 to 15 masks. Memory chips and complex logic chips need about 20 to 30 masks. Highly complex logic chips with numerous metal layers and high-frequency chips in BiCMOS technology require 30 to 40 masks.

The fewer masks required for the production of a chip, the better. This is so because each mask involves numerous additional production steps, such as applying photoresist, hardening photoresist, exposing or etching off photoresist. Firstly, these all harbor some probability of failure which potentially increases the scrap rate, and secondly they prolong the time of the wafer in the front-end fab and so also the time to market. And, on top of all that, each mask also costs money. Masks are the most expensive “material” used for chip manufacture. The cost for the complete mask set of a complex chip for a 65nm process meanwhile ranges at seven-digit level.

Mask manufacture is today a science in itself. The chrome structures are vapor deposited on the glass substrate in cleanroom processes. It is not least to the credit of the masks that we can today produce chip structures far smaller than the wavelength of the laser light used. The nature of the light is exhausted by performing breathtaking physical feats. On the one hand, the undesired light diffraction phenomenon is compensated by the mask (referred to as optical proximity correction) and, on the other, a phase shift of the lightwaves during passage through the glass substrate is attained by means of areas with varied glass thicknesses (phase change masks), which is used to control light intensity on the wafer surface. These are currently hot spots in mask manufacture. The cost of research and development can hardly be borne by semiconductor manufacturers alone.

(edited from IFX magazine Jan 26, 2007)

Front end, Back end

In the semiconductor industry all the process steps a wafer undergoes are called the front-end process, i.e. lithography, diffusion, ion implantation and applying the wiring levels. A wafer may pass through some stations several times, covering a distance of several kilometers in its up to seven-week odyssey. In the end the individual process steps may number as many as 500, all taking place in the front-end production hall, casually referred to simply as the front-end fab.

Front-end fabs are very capital-intensive. Furthermore, automation has reached a high degree. That’s why the labor cost does not make so great an impact on the manufacturing costs and front-end fabs are often also operated in high-wage countries.

Once the wafer has left the front-end fab, it goes to an intermediate storage facility, known as the “die bank”, and from there to the back-end fab. Here the second part of the chip manufacturing process begins. In the back-end process – taking one to two weeks – the wafer is cut up into individual ICs using lasers or dicing saws with diamond blades. They’re tested, assembled, re-tested and at the end they’re packed ready for dispatch.

Compared to front-end fabs, the labor cost in back-end fabs accounts for a larger share of the manufacturing costs. The machines are not as expensive and the proportion of manual work is higher. That’s why back-end sites are mostly located in low-wage countries.

Companies who have specialized exclusively on the front-end process are called foundries. The largest are TSMC, UMC (both in Taiwan), Chartered Semiconductor (Singapore) and SMIC (China).Companies who have specialized exclusively on the back-end process are called back-end subcontractors. The largest are Amkor (USA), ASE, Siliconware Precision (both Taiwan). There the specialization has already progressed to such a stage that some do only the testing and others only the assembly and packaging.
Mastery of front-end and back-end processes alike belongs to the concept of an IDM (Integrated Device Manufacturer). Infineon is an IDM of this kind. What’s more an IDM doesn’t just manufacture its chips, it also develops and markets them itself.

(extracted from IFX Emag 29 Nov 2006, Joe corner)

The rationale of chip production… or the way the cookie crumbles

At first glance the baker’s trade doesn’t have much to do with manufacturing microchips. Yet a closer look at the utilization of the prime production area – here the baking tray, there the wafer – reveals quite a few areas of common ground. The semiconductor industry definitely has the edge though.

Analysis of the baking process shows a high percentage of fixed production costs. These are accounted for firstly, of course, by the bakehouse premises (we would say fab) and secondly by the mixing and kneading machines and ovens (we say equipment). The variable costs for eggs, flour and grain (in our case wafers, gases, electricity, water) are negligible. So the machinery is in place, it just needs to be used as efficiently as possible. Optimization of the saleable products per baking tray is the name of the game.

The crux of the matter is to increase the number of cookies per oven charge. To achieve this, a first step would see simply placing the cookies closer to one another, concealing virtually the entire baking tray. We try to do that, too. The individual chips are so close together as to allow only the diamond saw-blade or laser beam to pass through. This scoring line between the chips – the so called kerf – is today only about 50 micrometers wide (about the thickness of a human hair).

A second step would see increasing the number of cookies by downsizing them – at the same selling price, of course. This recommendation would work as long as the customer still recognizes the cookies as such and accepts them. Increasing the number of chips at the expense of size is common practice. It’s called “shrinking” the chips. And here semiconductor technology has a peerless advantage over all other worldly goods: the smaller chip functions just as well as its larger precursor. When it comes to the enclosed end product you can’t even tell the difference between the two versions and so they can command the same price. (At least in theory. If the customer is aware that the chip is smaller and was therefore manufactured more economically, he’ll try to beat down the price). This pattern of chip evolution, that the smaller and cheaper (i.e. the chip proper and ultimately the transistors) fill the bill just as well as - and often better than - the larger and more expensive, was once dubbed “God’s gift to man” by the scientist Yuan Taur. No other technology has undergone shrinkage on anything like this scale, and by no means over a period spanning more than four decades. Were the cookies to have been systematically downsized over this length of time, their nutritional value would meanwhile be infinitesimal.

Once the exercise of downsizing the cookies has reached the crunch point, the third stage of optimization would be introduced: larger trays and perforce larger ovens. The step to a larger wafer is witnessed about every five to seven years. A larger wafer accommodates a higher number of chips. This is so firstly because it is simply larger. Secondly, the chips can fill the peripheral area better due to the reduced curvature. The changeover to larger wafers calls for new machinery all down the line, entailing significant investment.

The final tip: twenty-four-seven baking for better utilization of the machinery and ovens. This is a step the baker reluctantly accepts. Needless to say though, production in the chip industry operates in shifts, day and night. Economic reasons dictate that the multibillion-dollar machinery must not be left idle at any time.Getting to grips with the immense fixed costs hence requires vast quantities. It is imperative to use the most precious commodity, the wafer surface, as efficiently as possible. Therefore it is not without good reason that it’s occasionally also referred to as ‘real estate’.At ground-root level many of our colleagues are doing nothing other than the baker next door: baking smaller and smaller cookies to increase the output per tray. It just remains to be hoped that they’ll also sell like hot cakes!

(copy-paste from internal IFX emag: Joe corner)